1. Field of the Invention
The present invention generally relates to data identifying devices and light receivers, and particularly relates to a data identifying device and a light receiver which identify signals transmitted through digital-signal transmission lines.
With recent developments of optical communication technologies, an optical fiber technology has been introduced not only into trunk-line systems but also into subscriber-line systems, through which broadband information transmission for sending moving pictures and the like becomes available for households. As a result, such a scheme as fiber-to-the-home (FTTH) has been attracting attention to an extent that a feasibility study thereof has been conducted. A prerequisite for an introduction of the optical fiber technology into the subscriber-line systems is that the introduction be achieved at a low cost. Thus, there is a need to simplify the structure of transmitters and receivers compared to those used in the trunk lines, so as to reduce the number of adjustable factors of these devices.
2. Description of the Related Art
In the digital-signal transmission systems using optical fibers for transmitting digital signals, optical transit trunks are installed to provide inter-office transmission in the trunk-line systems. Light receivers of the optical transit trunks convert optical signals sent via the optical fibers into electric signals, and are equipped with an identifying circuit which identifies 0s and 1s of the converted digital signals. The identifying circuit generally adjusts a phase relation (i.e., relation of timing) between the data and an identifying clock used for identifying the data.
FIG. 1 is a block diagram of a light receiver of the related art. In FIG. 1, a light receiver 11 connected to an optical fiber 12 includes a light receiving device 13, an equalizer/amplifier circuit 14, a timing circuit 15, and an identifying circuit 16. The light receiving device 13 converts an optical signal transmitted through the optical fiber 12 into an electric current through a photoelectric process. The equalizer/amplifier circuit 14 amplifies the detected signal up to an identifiable level. The timing circuit 15 extracts an identifying clock, which is supplied to the identifying circuit 16 along with the amplified signal. The identifying circuit 16 identifies 0s and 1s in the amplified signal to generate identified data.
The phase relation between the identifying clock and the amplified data supplied to the identifying circuit 16 varies due to a variation in propagation speeds of signals through a transmission network. Thus, in order to assure an appropriate phase relation, the phase relation must be adjusted. The light receiver 11 used in the optical transit trunks often employs a coaxial cable for connecting between the timing circuit 15 and the identifying circuit 16, for example, so that an adjustment of the length of the coaxial cable can provide an appropriate phase relation. Also, there are known devices in which a phase relation is adjusted automatically through an application of the IC technology.
FIG. 2 is a block diagram of an automatic-phase-adjustment device of the related art.
An automatic-phase-adjustment device 21 shown in FIG. 2 is disclosed in a paper by Peter Cochrane et al. (IEEE Journal on Selected Areas in Communications, Vol. SAC-4, No.9, December, 1986). The automatic-phase-adjustment device 21 includes an S-R latch circuit 22, a delay unit 23, a differential amplifier 24, a D flip-flop 25, an S-R latch circuit 26, a comparator 27, a voltage-controlled phase shifter 28, and a clock extracting circuit 29. Input data is latched by the S-R latch circuit 22, which generates an output signal having a high level during a time duration corresponding to the delay time of the delay unit 23. This output signal is integrated by a resistance R1 and a capacitor C1, and, then, is applied to one input of the differential amplifier 24. Delayed input signal is applied to the D flip-flop 25 to generate identified data.
The identified data is applied to the S-R latch circuit 26, whose output signal is integrated by a resistance R2 and a capacitor C2 to be applied to the other input of the differential amplifier 24. An output of the differential amplifier 24 is a code-error signal which represents a difference between the pre-identified signal and the post-identified signal. The output of the differential amplifier 24 is compared with a reference voltage level by the comparator 27, an output of which is fed back to the voltage-controlled phase shifter 28.
Also, the input data is applied to the clock extracting circuit 29, where a clock signal is extracted from the input data to be supplied to the voltage-controlled phase shifter 28. The voltage-controlled phase shifter 28 is used for adjusting a phase of the clock signal based on the feedback signal mentioned above. The clock signal adjusted by the voltage-controlled phase shifter 28 is supplied to the D flip-flop 25, which uses the adjusted clock signal to generate the identified data.
In the automatic-phase-adjustment device 21 described above, in contrast with the case in which the coaxial cable is used, even if an optimal phase relation is changed because of changes in temperature-dependent or time-dependent characteristics of the circuits, a constant phase relation is maintained based on the signal feedback.
The automatic-phase-adjustment device 21 described above which is used for keeping an appropriate phase by controlling the phase of the clock signal through analog means results in a complexity of the circuit and a large power consumption. Thus, it is difficult to employ the automatic-phase-adjustment device 21 in the subscriber-line systems.
Since transmission distances in the subscriber-line systems are short (one to several kilometers) in comparison with inter-office transmissions, a large signal level can be used for light input to the light receiver 11. In this case, it is possible to obtain a large phase tolerance assuring desired characteristics of signals which the identifying circuit 16 receives. Thus, instead of using a phase control method based on analog processing, one clock signal can be selected from a plurality of prepared clock signals having different relative phases such that the selected clock signal is used for identifying the received signal. Such a method is disclosed in Japanese Laid-Open Patent Applications No. 1-233850 and No. 1-188050, which are hereinafter referred to as first and second references, respectively.
In the first reference, two clock signals having slightly different timing with each other are used for identifying a signal. Then, if results of the identifications are different between these two, it is determined that the two clock signals do not have appropriate phases so that the phases of the clock signals are inverted. In the second reference, a clock signal having a frequency double the data speed is prepared, and is frequency divided by a T-flip-flop which is reset at a leading edge of incoming input data. In this manner, the input data is identified by a clock having some time delay from the leading edge of the input data.
Identifying circuits of these two references can be implemented on logic circuits using gate arrays and the like. Thus, simple identifying circuits can be produced at a low cost.
In the first reference, however, when both of the two clock signals mistakenly identify data "0" as data "1", for example, these two clock signals are judged to be appropriate. Also, the identification results are sensitive to a time difference between the two clock signals and to a time difference between two signals applied to two identifying circuits (D flip-flops) after division of the input signal into the two signals. Thus, a design for very minute timing differences is required.
In the second reference, the clock signal having a frequency double the transmission speed of a transmission system is required. Thus, the entire system lacks a familiarity in a configuration thereof, and, also, has to be provided with a circuit for multiplying a frequency of the clock signal by a predetermined factor. As a result, the size of the circuit becomes large.
Other methods of identifying data are disclosed in Japanese Laid-Open Patent Applications No. 62-130037, No. 2-121431, and No. 3-293833.
In the above three references, input data is identified by using a polyphase clock. Since a phase of the clock is changed according to changes in the phase of the input data, synchronization processing is required for parallel signal processing in order to synchronize phases between different channels. Also, a number of clock signals should be prepared for a plurality of different phases. Thus, a timing design is difficult, and a circuit size becomes large.
In addition, a flexibility of selecting a transmission method is sacrificed because transmission codes usable in these three references are restricted to codes such as CMI (coded MARK inversion) codes for which an error detection is applicable.
Another method of identifying the input data is disclosed in the Japanese Laid-Open Patent Application No. 2-121431, in which input data is identified by combining identification results from a plurality of identifying units. In this method, even when outputs of the plurality of the identifying units are affected by each other, a phase of a clock to be selected is determined so that changing points of the identified data vary accordingly. Thus, a reliability of the system degrades significantly.
Accordingly, it is difficult to identify data while keeping an appropriate phase relation reliably between the data and a clock signal. Also, there is a problem of the circuits becoming complex and becoming a large size.
Accordingly, there is a need for a data identifying device and a light receiver which can generate identified data by using a simple circuit structure for keeping an appropriate phase relation between data and a clock signal.